Resolution of Interoperability challenges in Automatic Test Point insertion across different EDA vendors

Abstract: For a typical design there may be some design corners where ATPG tool/algorithm may find hard to generate patterns for fault detection. This leads to loss of coverage or increase in pattern count. To overcome this issue EDA tools(DFT/ATPG) provide options to insert Control logic on locations/nodes with poor controllability or Observe test logic on locations/nodes with poor observability, these are referred as Test Points. ATPG tools suggest Automatic Test Point (control/observe) along with insertion locations pertaining to following goals:

1. Coverage improvement
2. Pattern count reduction

Following are the two flows generally used for generating Automatic Test Points:

1. Automatic Test Point Generation at DFT insertion stage
2. Automatic Test Point Generation at ATPG stage

In both of the above cases the outcome will be a file having Test Point type and location where it has to be inserted (along with other relevant information dependent on tool eg. probable equivalent coverage improvement once the Test Point is inserted, number of faults targeted etc.). This file can be used by DFT insertion tool to insert suggested Automatic Test Points.

Challenge: All the three major EDA vendors provide DFT/ATPG tools, though one major issue in the above flow is that designers use DFT insertion tool from one EDA vendor and ATPG tool from other. So Automatic Test Point file generated from one EDA tool cannot be used as is by DFT insertion tool from other EDA vendor.

Organization of paper: This paper will first discuss different type of Test Points offered by EDA vendors followed by automatic Test Point file and their formats. Finally, a solution to the challenge will be discussed followed by conclusion.

Introduction

The control and observe Test Points offered by EDA vendors have different logical architecture (refer user guide of respective tool for further information on this). Following are the different types of Test points offered by major EDA vendors:

Control Test Points:

Tessent supported Control test Point: It is provides two types of control points:-

1. AND Control Point:
2. OR Control Point:

Control points are not going to change at capture cycles. The tool does not insert the AND and an OR control points in a same net, since these points are mutually exclusive.

12 Year-old Semiconductor IP and Design Services Company Receives New Investment

I have a transistor-level IC design background so was intrigued to learn more from the CEO of an IP and services company that started out in India 12 years ago. Last week I spoke with Samir Patel, CEO of Sankalp Semiconductor about the newest $5 million financial investment in his company from Stakeboat Capital Fund. The Stakeboat Capital Fund has some 28 years of investing experience and a current market capitalization above $8B.

I knew that the general trend was for IP companies to provide more specialized content along with design services to help speed new electronic products to market, but I didn't realize that there are some 200 IC design services companies around the world competing for this growing market segment. What makes outsourced IC design services attractive to OEMs are:

• Lower cost of development than hiring and training new engineers 
• Lower risk with a supplier that has a good track record
• Access to analog and mixed-signal IP blocks

Sure, there are giants in outsourcing like Wipro and Infosys, so what makes Sankalp interesting to me is their focus on analog and mixed-signal IP, something that is in strong demand these days as every IoT device with a sensor will require an AMS chip to get data into a digital format. The engineers at Sankalp have quite a broad range of experience to help speed the AMS parts or all of your next chip projects:

• Specification definition
• RTL design and verification
• SoC Implementation
• IP blocks
• AMS design
• Custom layout and P&R
• Technology Foundry Interface
• Validation and Characterizatio

Is there anything in VLSI layout other than “pushing polygons”?

Variation-Aware Design: A Hands-on Field Guide-calma-s140-gifAs I travel a lot in the last 15 years and visited customers as well as friends I was many times invited to talk to the Layout teams. The main purpose is always to encourage automation. So I developed a presentation related to market trend, technology trends, and latest tools advancements. In many cases I present updates from DAC (Design Automation Conference), to which I am a big fan participating for more than 20 years. From Memory to Analog and Digital Place & Route in all cases the first question was:

Is there anything else we can do other than just layout? What is my future? What can I do to grow faster? What did you do?

Everybody is afraid that there is nothing else but schematic to layout or Netlist to P&R and their life will be as monotone as a production line work. Nothing more wrong to think about.

In the last 3 years I decided to add an answer to this question and everywhere I talk to layout and design teams I reveal this in a last 20 minutes. So I decided this time to share this is with all of you so you will be able to act before I come to visit your company and present. Will write a series of articles describing the tools in which I was involved as a Layout Designer, from internal to external. Will use approximate timeframe, as some happen 30 years ago, and will provide some context of the condition that enabled such involvement. Will add names of people who actually did the work, or managed it as I was only the instigator, advisor, or tester in many cases.

There are a few condition that favorited my involvement in these developments:

• The Layout team encounters always the challenge of being the last in the chip design flow – so everything that is late or missed ahead in the design flow, falls on the layout team to "save the day". If and when the Management analyses the full flow it is obvious that the biggest issue is not layout creation but the ECO (Engineering Change Order) or changes to post layout simulations. So only when somebody looks at the full flow can understand that the sooner you bring layout (physical information) into circuit simulations the faster and more predictable gets the flow. From floorplan to placement, from routing to final layout clean from verification, layout is always "somehow" in the hot seat. So if you want change something work on the FLOW.
• I was a lucky guy to start working in MSIL (Motorola Semiconductor Israel). Our CEO at that time Zvi Soha cared only about tapeout (and at that time this meant a real tape 19 inch diameter going out with the final chip GDSII). He wanted MSIL to be the best site within Motorola Semiconductor, so he enabled internal cooperation between teams and supported any new tools development that can support his plan, even so sometimes against the corporate “policies”. Not too many companies even today, have meetings between CAD, Circuit Design, Layout Design, etc., to enable flow automation as a whole not only as a section of it. PMC Sierra with Norbert Diesing Mixed Signal CAD had a "cooperation group" for support and roadmaps, but no resources to build new tools.
• The hardware and software were all over the map. The front end design was divided in 2 sections: the system and functional simulations were done on IBM mainframe (cooled with water in a climate controlled room) and the circuit design was done on Daisy machines and software. The layout was done on Calma, a computer made by Data General (mainframe) with 4 terminals, each with 2 monitors, one text and one graphics. We did not have a mouse with 3 functions but a pen and a menu on the screen (taking very valuable visual rea). The pictures attached show a terminal of S-140 machine taken from the web.
• The verification was done on the IBM using a software called MASKAP, for which Motorola had the source code. So you had to write a tape from Calma and load onto IBM to run verification then write the results on tape and upload into Calma. We had a parser for the DRC images (errors polygons) on Calma screen and a printed error file to identify what is actually the error. A very tedious work I may say...
• I was a new immigrant to Israel and had problems with Hebrew. All the technology was in English so I focused on getting better at that, as this was a familiar language from my school days. The only way to move ahead was to add value to my knowledge, to be better at something that for others may not be of interest. Calma needed a workstation in the “cold room” the one with the server, so coming from Romania I was the most acclimatized to use it. We had shifts as we had 4 terminals and 8 people but if you used the cold room terminal you can stay longer without bothering others. So I started to read all Calma manuals, in 3 months I knew enough to be "dangerous".

Addressing Clock Tree Synthesis Challenges

Debaprasad Daxiniray & Chinmaya Masali (Sankalp Semiconductor)

Abstract:

Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.

Clock tree network enables in making design clean from a timing perspective. However, it is responsible for more than one third of the total power consumption of the chip. The impact of variations in the clock path is more than 2 times the other paths in the design. These variations in-turn affects the timing paths. Let us take an example; Due to the variation, if the clock path to the launching register is slowed down by 100ps and the clock path to the capturing register is fastened by 100ps then it impacts the setup constraint by adding 200ps more to it, this in-turn affects the timing path by making it more critical. Here we can see the importance of building a balanced clock tree. We will discuss on the timing improvements and methods to reduce the variations in the clock tree. The steps followed in building a customized clock tree and the steps followed to bring down the variations in the clock tree has been depicted in the following sections.

1. Addressing design challenge of registers placed far apart

The section describes the problem encountered and fixes while building the clock tree when registers are far apart. Referring to the diagram (Figure-1) below the clock port is positioned at the middle of the bottom part of the chip. The encircled part at the bottom of the chip represents the digital glue logic that is communicating with the digital logic (beside analog block) at the top of chip. There are large magnitude of setup violations observed on these paths. Being a full chip design, the output delay was critically constrained that led to large timing violations on the output pads. Here are some methods targeted to meet setup timing by building a customized clock tree.

Automatic clock Tree Synthesis Technique

With Automatic clock tree synthesis, the CTS engine puts a lot of buffers across the chip that are not desired. The registers near the clock port face large insertion delays. This effect is due to the clock balancing nature of automated CTS engine. The Clock tree structure will be H-tree similar to the figure-1. Since the chip size is large, the number of buffers are huge on the clock tree due to clock balancing. This renders the experiment not to be useful.

Dan Clein's status of Virtuoso, Custom Compiler, and Pulsic tools

I really liked Marmaduke's AMS circuit designer's DAC Trip Report. I've not seen anything with this level of AMS detail on the web anywhere. Please tell him that "Dan Clein says 'Good Job!'" from me, OK? Since that DAC was 10 months ago, I thought I'd share my State of the Union on what's going on with full custom layout EDA tools now.

Right now, Mentor does not have anything below 28nm (FinFET country) for full custom layout. Wally purchased Pyxis a few years ago, with the intention to be OA ready, but the results are not very encouraging...

Mentor Pyxis (router)

• Helped develop an OA platform inside Mentor
• Has iPDK's for TSMC, Tower, GF... but only down to 28 nm
• The Pyxis router is good - as it is the original engine

IC Station (placer)

• older technology. Not originally an OA tool.
• it's a device placer with only limited capabilities; not really powerful like the schematic option.
• IC Station is not 100{6840d83bd39e1f667912dd82873565e355733b93d0f9fc0850650a5f8436df67} OA compatible, but still has the Correct By Construction mode available
• the Pycell device generator is working now, but as a cell/MAP ROD AMPLE code

Tanner Tools

• low cost option that shines in MEMS applications

Mentor is still trying to figure out how to use Tanner tools better, but them integrating it into their old IC Station is not very likely. The only shiny star for Mentor is their Calibre family tools. From physical verification to parasitic extraction, Calibre is still the leader all the way down to 5nm...

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