Technology Foundation

Memory Complier & Touchstone

Memory Complier & Touchstone

MC2, an automated and proven memory development system, targets embedded and discrete memories. MC2 automates the overall methodology for the design and distribution of memories, helping designers create solutions more rapidly. Empowering memory designers to design new memory instances, leverage existing designs, target new processes, create new memory architectures, MC2 increases productivity and promotes the reuse of design IPs. MC2 offers unique scalability for density as well as seamless migration to new sub-micron processes.

Customers using MC2 are expected to save over 40% of their development resources and time in the first project alone. Incremental savings can be expected over time. In addition, MC2 generates reusable memory architecture for secure distribution to ASIC & SoC designers.

Reusable-Memory-Architectur

Touchstone is a characterization solution that provides timing and power parameters. The solution performs characterization at Instance (cell to lib) and compiler level and can be seamlessly integrated into any custom environment. The method of specification of characterization vectors is based on high level operations, e.g. read, write, etc. Tightly coupled with MC2, Touchstone provides options to present trends of calculated parameters.

Compiler-Characterization-V

 

Customer Success Stories

Automotive

  • Design & Verification of Automotive Dashboard SoC

Consumer

  • Turnkey Development of eDisplayPort 1.4b Rx
  • Compatible to RBR, HBR and HBR2 rates.
  • Design Architecture for COG application at HBR2 rates
  • Modelling eDP cable, connector and COG interconnect

IoT

  • Industrial energy metering system
  • End-to-end system definition and development
  • Support for mass manufacturing

Foundry

  • Standard Cell Library Development in 7nm
  • Spec to GDSII
  • ARM Cortex M3 with mixed Vt
  • Module & Top level verification of
  • Memories, Test & Efuse

Networking

  • Verification of Dual ARM SoC
  • Key Highlights
  • Verification Planning Test
  • Testbench development in SV/UVM & C
  • Performance & Low Power Verification